Call us toll-free

Logic Synthesis for Large Pass TransistorCircuits.

VIS: A System for Verification and Synthesis.

Approximate price

Pages:

275 Words

$19,50

Logic synthesis for large pass transistor circuits

N2 - With the shrinking feature sizes and increasing transistor counts on chips, the push for higher speed and lower power makes it necessary to look for alternative design styles which offer better performance characteristics than static CMOS. Among them, pass transistor logic (PTL) circuits give great promise. Since the delay in a pass-transistor chain is quadratically proportional to the number of stages, and a signal may degenerate when passing through a transistor, buffers are necessary to guarantee performance and restore signal strength in PTL circuits. In this paper, we first analyze the effects of buffer insertion on a circuit and give the sufficient and necessary condition for safe buffer insertion. Then the buffer minimization problem is formulated, which asks for a minimum number of buffers to make sure that no path has length longer than a given upper bound. Although NP-hard in general, we show that, when buffers are required on multiple fan-outs, it can be solved linearly. We also consider the case when buffers are inverters, where phase assignment need to be done with buffer insertion. Experiments are done on MCNC logic synthesis and optimization benchmarks; compared with a level-by-level insertion, a large number of buffers are saved.

Simulation will be done to verify the functionality and synthesis will be done to get the NETLIST.

...s approaches based on Pass Transistor Logic (PTL) BDDs seem to be a good starting point. First promising results on how to transform a decision diagram to a circuit based on PTL have been reported in =-=[24, 9, 3]-=-. One drawback ofBDDs is that they are very sensitive to the variable ordering, i.e. the size of the representation may vary from linear to exponential. Therefore in the last few years several methods...

Logic synthesis for pass-transistor design - ResearchGate

Tripathy and Rajeev Tripathi,

This work focuses on logic synthesis and optimization tools for ultra-low power pass-gate circuits mapped into emerging technologies, Graphene and silicon nano-wires. More specifically, we describe a novel multi-function decomposition engine that (i) efficiently performs abstract circuit modeling through a highly-compact data structure called Multi-Function Pass Diagram (MFPD), (ii) provides an effective multi-gate synthesis & optimization flow, (iii) allows accurate power/delay estimations. The contents reported in the following sections represent one of the first examples of how dedicated algorithms and data-structures can substantially improve the quality-of-design when moving from CMOS to emerging technologies.

P. Buch, A. Narayan, A. Newton, and A. Sangiovanni-Vincentelli, Logic synthesis for large pass transistor circuits. IEEE/ACM International Conference on Computer-Aided Design, November (1997), pp. 663–670.

Top-down pass-transistor logic design - IEEE Xplore …

Index Terms — Adder circuits, CPL, complementary CMOS, low-voltage low-power logic styles, pass-transistor Pertenece a  Autor(es)

T.-T. Liu, L. Alarcón, M. Pierson, and J. Rabaey, “Asynchronous computing in sense amplifier-based pass transistor logic,” in Proc. 14th IEEE Int. Symp. ASYNC, Apr. 2008, pp. 105–115.

AB - With the shrinking feature sizes and increasing transistor counts on chips, the push for higher speed and lower power makes it necessary to look for alternative design styles which offer better performance characteristics than static CMOS. Among them, pass transistor logic (PTL) circuits give great promise. Since the delay in a pass-transistor chain is quadratically proportional to the number of stages, and a signal may degenerate when passing through a transistor, buffers are necessary to guarantee performance and restore signal strength in PTL circuits. In this paper, we first analyze the effects of buffer insertion on a circuit and give the sufficient and necessary condition for safe buffer insertion. Then the buffer minimization problem is formulated, which asks for a minimum number of buffers to make sure that no path has length longer than a given upper bound. Although NP-hard in general, we show that, when buffers are required on multiple fan-outs, it can be solved linearly. We also consider the case when buffers are inverters, where phase assignment need to be done with buffer insertion. Experiments are done on MCNC logic synthesis and optimization benchmarks; compared with a level-by-level insertion, a large number of buffers are saved.

Pass Transistor Logic Reference | Cmos | Electronic …
Order now
  • Decision Diagrams and Pass Transistor Logic Synthesis

    Pass transistor logic (PTL) can be a promising alternative to static CMOS for deep sub-micron design

  • Logic Synthesis for Large Pass Transistor Circuits | …

    Abstract Pass transistor logic (PTL) can be a promising alternative to static CMOS for deep sub-micron design

  • / Buffer minimization in pass transistor logic

    CiteSeerX - Scientific documents that cite the following paper: Decision Diagrams and Pass Transistor Logic Synthesis

Order now

of proper driving capability designed pass-transistor logic

This chapter deals with metal–oxide–semiconductor (MOS) combinational circuits. The operation of pass-transistor logic circuits based on switch logic is explained and advantages and limitations of pass-transistor logic circuits are highlighted. The different members of pass-transistor logic family are introduced. The static and switching characteristics of multi-input NOR and NAND gates based on gate logic are discussed in detail. The operation of MOS dynamic circuits are explained and charge sharing and charge leakage problems associated with MOS dynamic circuits are introduced. The clock skew problem of MOS dynamic circuits is also discussed. The operation of domino-complementary metal–oxide–semiconductor (CMOS) and (NO Race) NORA-CMOS dynamic circuits is explained. Realization of several example functions, such as full adder, parity generator, and priority encoder, using the three logic styles is considered and their area and delay are compared.

Pass-transistor logic design References; Citations ..

R. Shelar and S. Sapatnekar, BDD decomposition for delay oriented pass transistor logic synthesis. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13, 957 (2005).

A general method in synthesis of pass-transistor ..

With the shrinking feature sizes and increasing transistor counts on chips, the push for higher speed and lower power makes it necessary to look for alternative design styles which offer better performance characteristics than static CMOS. Among them, pass transistor logic (PTL) circuits give great promise. Since the delay in a pass-transistor chain is quadratically proportional to the number of stages, and a signal may degenerate when passing through a transistor, buffers are necessary to guarantee performance and restore signal strength in PTL circuits. In this paper, we first analyze the effects of buffer insertion on a circuit and give the sufficient and necessary condition for safe buffer insertion. Then the buffer minimization problem is formulated, which asks for a minimum number of buffers to make sure that no path has length longer than a given upper bound. Although NP-hard in general, we show that, when buffers are required on multiple fan-outs, it can be solved linearly. We also consider the case when buffers are inverters, where phase assignment need to be done with buffer insertion. Experiments are done on MCNC logic synthesis and optimization benchmarks; compared with a level-by-level insertion, a large number of buffers are saved.

Why use pMOS in pass transistor logic?

Simulation run conducted on different benchmarks demonstrate that pass-gate circuits synthesized with the proposed tool are smaller and shallower, hence less power hungry and faster than circuits obtained through conventional synthesis methodologies based on standard design flows. As an additional contribution, the results prove that our solution is not only applicable to beyond-silicon technologies but also to standard MOSFETs.

Order now
  • Kim

    "I have always been impressed by the quick turnaround and your thoroughness. Easily the most professional essay writing service on the web."

  • Paul

    "Your assistance and the first class service is much appreciated. My essay reads so well and without your help I'm sure I would have been marked down again on grammar and syntax."

  • Ellen

    "Thanks again for your excellent work with my assignments. No doubts you're true experts at what you do and very approachable."

  • Joyce

    "Very professional, cheap and friendly service. Thanks for writing two important essays for me, I wouldn't have written it myself because of the tight deadline."

  • Albert

    "Thanks for your cautious eye, attention to detail and overall superb service. Thanks to you, now I am confident that I can submit my term paper on time."

  • Mary

    "Thank you for the GREAT work you have done. Just wanted to tell that I'm very happy with my essay and will get back with more assignments soon."

Ready to tackle your homework?

Place an order