on modeling the effect of aging mechanisms on flash memory and SRAM.
(2014) Modeling and design of high speed SRAM based memory chip. MTech thesis.
VLSI IMPLEMENTATION OF 32KB SLEEPY SRAM THESIS
Pavlov A thesis presented to the University of Waterloo in fulﬁllment of the thesis requirement for the degree of Design of Address Decoder and Sense Amplifier for SRAM Address decoder and sense amplifier is important component of SRAM memory.
SRAM is used as Cache memory which is very fast and used to speed up the task of processor and memory interface. With improvements in VLSI technology, processor speeds have increased. The improvements in SRAM speed of operation with increased integration, bigger sizes, technology shrinking and power dissipation is required to match with improved processor. 2kb SRAM block is designed and tested for proper read and write operation. The single SRAM cell, the 32x32 memory array, along with the decoder circuit, the sense enable and write enable logic, are placed out. The different critical paths of the system, comprising of the row and the column decoder, the column mux and the read-write circuits are recognized and sized to meet the target specifications. Simple model for distributed interconnect delays, is introduced and verified by Cadence simulations, their necessity is demonstrated. The models for the delay of a SRAM are used to determine the array sizes for a SRAM. An analytical delay model is proposed to predict the block size for SRAM; proposed model is based on dynamic strategies for word line charging and bit line discharging. Novel Sense Amplifier (SA) circuit for 2kb SRAM is presented and analyzed in this work. Sense amplifier using decoupled latch with current controlled architecture is proposed and compared with Current controlled latch SA using 90nm CMOS technology. Delay and power dissipation in proposed SA is 21.5% and 18.5% less than that of the current controlled SA. Butterfly architecture that is central decoding scheme is used to make a 2kb block from 1kb, after simulations, the maximum operating frequency of the system was found to be 800MHz.
An SRAM memory cell is a bi-stable ..
This thesis addresses these challenges and propose different solutions at the device, circuit and architecture levels in traditional SRAMs and emerging spintronics memories.
Based on the fact that SRAMs are the dominant structure in cache memories, which strongly impact the overall power, performance, and area of the embedded computing systems, two solutions are proposed to reduce these challenges.
Design of High Performance SRAM Based Memory Chip
Modeling and design of high speed SRAM based memory chip
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