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AB - This paper proposes a software/hardware co-design system for a Trax solver. Since development with Hardware Description Language (HDL) is tough work, we selected an approach: 1. writing C++ code, 2. finding bottleneck of the problem, and 3. re-writing the bottleneck part in the High Level Synthesis(HLS). Generally, game AI algorithm is divided into 3 parts, data structure, searching, and board evaluation. In this design, we focused on the data structure and implemented an incremental update algorithm. As a result, we can detect a line and an attack with O(1). Also, we implemented a local pruning, which reduces search area when the search depth becomes large in alpha beta tree search. The implemented solver works with 150MHz clock on Xilinx XC7Z020-CLG484 of Digilent ZedBoard.

System Design Journal. Help and solutions for tomorrow's design. by Ron Wilson, Editor-in-Chief

N2 - This paper proposes a software/hardware co-design system for a Trax solver. Since development with Hardware Description Language (HDL) is tough work, we selected an approach: 1. writing C++ code, 2. finding bottleneck of the problem, and 3. re-writing the bottleneck part in the High Level Synthesis(HLS). Generally, game AI algorithm is divided into 3 parts, data structure, searching, and board evaluation. In this design, we focused on the data structure and implemented an incremental update algorithm. As a result, we can detect a line and an attack with O(1). Also, we implemented a local pruning, which reduces search area when the search depth becomes large in alpha beta tree search. The implemented solver works with 150MHz clock on Xilinx XC7Z020-CLG484 of Digilent ZedBoard.

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This paper proposes a software/hardware co-design system for a Trax solver. Since development with Hardware Description Language (HDL) is tough work, we selected an approach: 1. writing C++ code, 2. finding bottleneck of the problem, and 3. re-writing the bottleneck part in the High Level Synthesis(HLS). Generally, game AI algorithm is divided into 3 parts, data structure, searching, and board evaluation. In this design, we focused on the data structure and implemented an incremental update algorithm. As a result, we can detect a line and an attack with O(1). Also, we implemented a local pruning, which reduces search area when the search depth becomes large in alpha beta tree search. The implemented solver works with 150MHz clock on Xilinx XC7Z020-CLG484 of Digilent ZedBoard.

"The C-to-Silicon Compiler very effectively handles mixed control/datapath designs, as well as incremental synthesis," said Steve Svoboda, product marketing director at Cadence. "In response to several customer requests this year, we applied our unique ELS technology to designs targeting the Altera and Xilinx FPGA families like we did with Cadence RTL Compiler. As a result, customers now get the same advantages with high-level synthesis whether they are targeting their designs to FPGAs or to ASICs."

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